BUS ARCHITECTURE

BUS ARCHITECTURE

A set of parallel conductors, which allow devices attached to it to communicate with the CPU is called BUS. It allows information and signals to travel between components. The bus consists of three main parts.

• Control Lines

• Address Lines

• Data Lines

Control lines- These allow the CPU to control which operations the devices attached should perform, I.E. read or write. These are used to synchronize and co ordinate the operation of CPU with other devices.

Address lines -Allows the CPU to reference certain (Memory) locations within the device. Specifies the location of the device .The number of bits in the address bus represents the number of physical locations that the CPU can access.

Data lines -The meaningful data which is to be sent or retrieved from a device is placed on to these lines. The size of a data bus is typically 8, 16, 32, and 64 bits. The Bus is set to run at a specified speed which is measured in MHz .The main differences among buses are amount of data transfer & the speeds so BUS is always differentiated or given a different name on the basis of their speed, devices with which BUS is connected and amount of data they can transfer.

The System Bus

The system bus is a series of high-bandwidth pathways that connect the CPU to memory, the level 2 (L2) cache and the I/O buses. The purpose of the system bus is to get information to and from the CPU at the fastest rate possible. As a result, the system bus is the fastest bus in the computer, with speeds up

to 800 MHz on current motherboards. In fact, the system bus speed is more commonly referred to as the motherboard speed (with the CPU running at a multiple of this speed).

The systems bus actually consists of several buses, connected by several controller chips as follows:

The front side bus is actually a combination of 2 other buses:

• The processor bus is the highest-level communication pathway between the CPU and the

Northbridge chip;

• The memory bus is a direct pathway between the memory controller and the Northbridge chip.

The backside bus is a special bus that connects the CPU to the level 2 (L2) cache. (Both of which are often packaged together in the same module). As a result, this bus is also called the cache bus. Unlike the rest of the system bus components, the cache bus is a dedicated bus that runs at or near the CPU speed, achieving better performance for caching operations.

When buses terminates on the motherboard ,a slot/port is placed to provide connectivity between bus and the card which will be attached with the slot and as a result a path will be provided from circuit to CPU with the help of BUS. Various developments took place in terms of speed and width of bus i.e. 16bit, 32 bit etc and accordingly they were given different name. We will study various type of bus that has been developed till date .these will be differentiated mainly on the basis of their speed, use and width. The slot that is placed on the bus to provide connectivity is known as slots like PCI bus was developed in terms of more speed and the slot placed on the bus is named as PCI slot. So either we study various BUS type or different type of slot both amounts to same as far as data transfer speed is

concerned.

The differences between computer buses break down into these categories:

Data width & Cycle rate - The data width and cycle rate are used to determine the bandwidth, or

the total amount of data that the bus can transmit. An 8-bit bus (1-byte data width) that operates at a

cycle rate of 1,000 MHz (1,000,000 times per second) can transfer 8 Mbps (1 MBps).

Device management & Type -The device-management specification indicates the maximum

number of supported devices and the difficulty of configuring them. There are two types of bus

communications, serial and parallel. On a parallel bus, all devices have their own interface to the bus,

which is the norm. Serial devices are tied together in, well, a series; the last one has to talk “through” the first one. This can cause obvious performance problems. These busses typically are used in conditions where data throughput isn’t critical.

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